----------------------------------------------------------------------------------
-- Company: Residencia	
-- Engineer: Leonardo Araujo dos Santos
-- 
-- Create Date:    16:40:33 01/05/2010 
-- Design Name: 
-- Module Name:    RegistersFile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
-- This register file will store 16 n bits registers, one write port and two 
-- read ports(A and B).
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- General package
use work.GeneralProperties.ALL;

entity RegistersFile is
    Port ( --CLK : in  STD_LOGIC;
           InputPort : in  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           OutPortA : out  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
           OutPortB : out  STD_LOGIC_VECTOR ((bus_size - 1) downto 0);           
           WriteEnable : in  STD_LOGIC;
           WriteAddress : in  ProcessorRegisters;
			  ReadAddPortA : in  ProcessorRegisters;
           ReadAddPortB : in  ProcessorRegisters;
           ReadAEnable : in  STD_LOGIC;
           ReadBEnable : in  STD_LOGIC);
end RegistersFile;

architecture Behavioral of RegistersFile is
  subtype reg is std_logic_vector((bus_size - 1) downto 0);
  type regArray is array (0 to (reg_file_size-1)) of reg;
  signal RF : regArray;
begin
  
  WriteProcess : process (WriteEnable)
  begin    
	 if (rising_edge(WriteEnable)) then 
      RF(reg2int(WriteAddress)) <= InputPort;
    end if;	 
  end process;
  
  ReadPortA : process (ReadAEnable,ReadAddPortA,RF)
  begin
    if (ReadAEnable = '1') then
	   OutPortA <= RF(reg2int(ReadAddPortA));
	 else
	   OutPortA <= (others => 'Z');
	 end if;
  end process;
  
  ReadPortB : process (ReadBEnable,ReadAddPortB,RF)
  begin
    if (ReadBEnable = '1') then
	   OutPortB <= RF(reg2int(ReadAddPortB));
	 else
	   OutPortB <= (others => 'Z');
	 end if;
  end process;

end Behavioral;

